Addendum to “Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches”

Abstract The MICRO 2011 paper “Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches” proposed a novel die-stacked DRAM cache organization embedding the tags and data within the same physical DRAM row and then using compound access scheduling to manage the hit latency and a MissMap structure to make misses more efficient. This addendum provides a revised performance analysis, an updated performance analysis using more up-to-date timing and system parameters, and also provides additional analysis on the performance of the system. The analysis shows that Compound Access Scheduling (CAS) and the MissMap are still effective, but not as effective as we originally found. Based on the original parameters used in the MICRO’11 paper, a 1GB DRAM cache with CAS and a MissMap provides approximately 25-50% of the performance benefit, rather than about 80% as previously reported, of an impractical DRAM cache implementation using SRAM tags depending on cache size (128MB-1GB). Based on more up-to-date parameters, the CAS and MissMap approach provides about 50-60% of the benefit compared to the SRAM-tags approach.